1) Field of the Invention
The present invention relates to an asynchronous data transmitting apparatus.
2) Description of the Related Art
Asynchronous data transmitting apparatuses includes a transmitter and a receiver that are connected via parallel transmission lines. The transmitter transmits data signals to the receiver by a transmit clock and a receive clock and the receiver receives the data signals by a receive clock. In other words, the transmitter and receiver operate asynchronously from each other.
FIG. 16 is a block diagram of a conventional asynchronous data transmitting apparatus. FIG. 17 is a timing chart to explain the data receiving when a skew occurs in the data of the asynchronous data transmitting apparatus shown in FIG. 16. A transmitter 100 and a receiver 200 are connected, for instance, via three signal transmission lines 301, 302, and 303 that are parallel transmission lines. A transmit clock CLOCK_A of the transmitter 100 and a receive clock CLOCK_C of the receiver 200 are generated independent of each other with no fixed phase relation between the CLOCK_A and the CLOCK_C.
In the transmitter 100, three flip-flops 111, 112, and 113 form a synchronous circuit and read three bits of transmitted data of DATA_0, DATA_1, and DATA_2, in synchronization with the CLOCK_A. Moreover, the flip-flops 111, 112, and 113 deliver the transmission data to signal transmission lines 301, 302, and 303, as data of DATA_0A, DATA_1A, and DATA_2A, respectively.
In the receiver 200, three flip-flops 211, 212, and 213 form a synchronous circuit and read transmission data of DATA_0B, DATA_1B, and DATA_2B from the three signal transmission lines 301, 302, and 303, in synchronization with the CLOCK_C. Moreover, the flip-flops 211, 212, and 213 deliver the data read to a processing system, as data of DATA13 0C, DATA_1C, and DATA_2C.
In such an asynchronous data transmitting apparatus, the transmitter and receiver communicate control signals in order to acquire an appropriate timing for the transmitting or the receiving. Therefore, since the receiver allows the receiving of the data signal at the time when receiving the control signals from the transmitter, there is no problem with a data delay time on the signal transmission lines.
However, in the asynchronous data transmitting apparatus, the timing when the transmission data changes and the timing when the data is read by the receive clock are completely asynchronous. Hence, at times, a reading edge of the receive clock comes in a period when the transmission data changes. As a result, following two problems arise.
The first problem is as follows. When the data to be read in the flip-flops completely overlaps with the timing of data reading, the data reading remains incomplete. As a result, a metastable state occurs in which the output of the flip-flops ends up with an intermediate potential, and the changed signals are reconverted to the original state.
The second problem, even though it may not cause metastability, is as follows. If in the parallel transmission lines, which transmit the plural bit data in parallel, the delay amount differs in each of the transmission lines, then at times the timing of data reading between the parallel databits may precede or follow the timing when the data changes. Thus, as shown in FIG. 17, a combination of such databits is received which do not exist at the transmitting end. The difference in the data delay amount is called a skew. A detailed explanation of the reception operation when a skew occurs in the data of the asynchronous data transmitting apparatus is given next with reference to FIG. 17.
The transmitter 100 sends, as the transmission data DATA_2A, DATA_1A, and DATA_0A, databits “100”, “011”, and “100” in the same sequence, in synchronization with the transmit clock CLOCK_A. The three signal transmission lines have different delay amounts. The delay amount in the signal transmission lines goes on increasing in the sequence of the signal transmission line 303 that carries the transmission data DATA_0A, the signal transmission line 302 that carries the transmission data DATA_1A, and the signal transmission line 301 that carries the transmission data DATA_2A.
As a result, the time at which the change of databit occurs is different in the transmission data DATA_2B, DATA_1B, and DATA_0B reaching the receiver 200. That is, the change takes place earliest in the transmission data DATA_0B, then in the transmission data DATA_1B, and last in the transmission data DATA_2B. The receiver 200 reads the transmission data in the sequence DATA_2B, DATA_1B, and DATA_0B at a data reading timing 401 that is in synchronization with the leading edge of the receive clock CLOCK_C.
At this time, in the first transmission data DATA_2B, DATA_1B, and DATA_0B, the data reading timing 401 falls after the change in the databits. Consequently, the databit of the reception data DATA_2C, DATA_1C, and DATA_0C will be the same as the databit of the transmission data, namely “100”.
However, in the second transmission data DATA_2B, DATA_1B, DATA_0B, the data reading timing 402 precedes the transition point in the transmission data DATA_2B whereas it falls after the transition point in the transmission data DATA_1B and DATA_0B. Consequently, the databits of the reception data DATA_2C, DATA_1C, and DATA_0C become “111”, as compared to the databit “011” of the transmitting end. As a result, the receiver receives an incorrect data and consequently performs an incorrect operation.
A number of ideas as well as preventive measures have been proposed for circumventing the first problem, that is, the metastable state. However, regarding the second problem, that is, a skew between the data, it is practically not possible to eliminate the problem completely as the timing of the receive clock cannot be predicted. An incorrect data is read in the asynchronous data transmission when there is a skew between the data and when the reading of data and the change in data coincidentally occur at the same time. Thus, the probability that an incorrect data is read is very low.
Consequently, the conventional technologies, as disclosed in Japanese Patent Application Laid-Open No. 6-54016 (hereinafter, “first conventional art”) and Japanese Patent Application Laid-Open No. 4-178047 (hereinafter, “second conventional art”), focus on reducing the skew between the data as much as possible and thereby reducing the probability of reading an incorrect combination of data at the receiving end.
In the first conventional art, a skew correction circuit is disclosed, which includes a detecting unit that detects, from edges that must have the same timing, the edge of one transmission signal from among plural transmission signals transmitted by parallel transmission lines, a correction signal generating unit that generates correction signals according to the edge cycle of the edge detected by the detecting unit, and a correction unit that synchronizes the edges of the plural transmission signals with the correction signals generated by the correction signal generating unit and then outputs in synchronization all those edges.
In the second conventional art, a skew correction system for obtaining a skew-corrected data is disclosed, which includes a skew measurement signal pattern detecting circuit-cum-skew value detecting circuit that detects, after receiving from the receiving end the predetermined data set beforehand, the delay amount of the data with maximum phase advancement, a control circuit that outputs a control signal to correct the delay amount, based on each delay amount detected by the skew measurement signal pattern detecting circuit-cum-skew value detecting circuit, and a skew correction circuit that selects and outputs, from among the parallel outputs, the data on which skew correction is carried out by the control signal.
As the asynchronous data transmission is employed in a semiconductor integrated circuit, care is always taken when designing the transmission line. However, it is still practically not possible to reduce the skew between the data occurring in the parallel transmission lines to zero. As a large number of asynchronous data transmissions are employed in the recent large-scale semiconductor integrated circuits, it is not possible to ignore the problem of a skew between the data and incorrect operations may frequently occur as a result inside the apparatus itself. However, especially in case of the large-scale semiconductor integrated circuits, provisions made to eliminate incorrect data reading due to a skew between the data are insufficient. Thus, active measures to find a fundamental solution are expected in order to avoid incorrect data reading.